Integrated circuits are widely used in communication systems for performing time-based operations and sequential operations. A phase-locked loop (PLL) is used to generate an oscillator (or an output) signal based on an input reference signal. The output signal has a phase that is directly related with a reference phase of the reference signal. PLLs are widely used in modern electronic systems such as radios, telecommunication systems, computers, and so forth. In communication systems, the PLLs are used to generate oscillator signals, which are used for modulation and demodulation of a message signal. The PLL includes a phase detector, a charge pump, a filter, and a voltage-controlled oscillator (VCO). The phase detector compares the phase of the output signal with the reference phase of the reference signal and generates a phase error signal. The charge pump receives the phase error signal and generates a corresponding current signal. The filter receives and smoothens the current signal and provides a voltage control signal to the VCO. The VCO generates the output signal having an output frequency that is proportional to a reference frequency of the reference signal.
Typically, the VCO is implemented using an inductive-capacitive (LC) VCO (LCVCO). The LCVCO includes a cross-coupled differential amplifier with an LC tank in the feedback path. The LC tank includes an inductor, a varactor, and switched capacitor banks. The switched capacitor banks extend the tuning range of the LCVCO. The precise control of the output frequency is important for overcoming jitters in the PLL.
Further, the PLL may include multiple VCOs, such as a low-frequency VCO (LFVCO), a medium-frequency VCO (MFVCO), and a high-frequency VCO (HFVCO), that are designed to operate in different frequency ranges and generate output signals in corresponding frequency ranges. In an example, the LCVCO may operate in a first frequency range (e.g., 2.7 GHz-3.7 GHz), the MFVCO may operate in a second frequency range (e.g., 3.7 GHz-4.7 GHz), and the HFVCO may operate in a third frequency range (e.g., 4.7 GHz-5.7 GHz). Such PLL can generate the output signal over a wide range of frequencies i.e., 2.7 GHz-5.7 GHz, by selecting one or a combination of the LFVCO, MFVCO, and HFVCO. However, certain applications may require an oscillator signal having a much lesser frequency, i.e., less than 2.7 GHz. In such cases, the PLL fails to generate the oscillator signal at such a lower frequency (e.g., less than 2.7 GHz).
Generally, for matching the output frequency with the desired frequency, the VCO (e.g., the LFVCO, MFVCO, or HFVCO) is required to be calibrated. The PLL uses a digital-to-analog converter (DAC) for calibrating the VCO such that the output frequency matches the desired frequency. A capacitive DAC is commonly used which calibrates the VCO based on a set of calibration bits such that the output frequency matches the desired frequency. However, achieving a wide frequency range using a single VCO is difficult because the capacitive DAC operates at a higher capacitance (i.e., lower oscillator frequency) and hence, the effective frequency steps decrease, thereby requiring significantly higher number of bits to implement lower frequencies. Further, it is difficult to implement a PLL having a wide-tuning range due to channel leakage and degradation. Further, the jitter level in the PLL increases due to the variations in process, voltage, and temperature (PVT). Therefore, the PLL, especially, the PLL with multiple VCOs is prone to degrade in performance due to the PVT variations. Further, the jitter results in timing errors in the integrated circuit that receives the output signal from the PLL. In certain scenarios, the PLL includes analog circuits for compensating the output frequency of the PLL due to the PVT variations. However, one disadvantage of such a PLL is the limited range of frequency that it can generate due to the additional analog circuits.
Further, in such an implementation of PLL with multiple VCOs, a frequency range of one VCO may overlap with a frequency range of the other VCO. Tuning the frequency impacts a gain factor of the corresponding VCO, thereby leading to suboptimal performance of the PLL. Compensating for changes in the VCO gain factor can be more complicated.